1. Field of the Invention
This invention is related to the field of processors and, more particularly, to decoding instruction information in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications that may benefit from 64 bit address or operand sizes.
x86 instructions have the ability to specify a displacement value and an immediate value. In current implementations of the x86 architecture, displacement and immediate values can be up to 32 bits. Generally speaking, displacement values are used to generate addresses and immediate values are used to generate a numerical result. In architectures where the address and operand sizes increase beyond 32 bits, larger bit sizes of displacement and immediate values may become desirable. It would be desirable for instructions to be able to specify displacement and immediate values larger than 32 bits while using an existing instruction format.
The problems outlined above are in large part solved by an apparatus and method for generating 64 bit displacement and immediate values. In a given processor architecture such as the x86 architecture, instructions may conform to a specified instruction format. The instruction format can include a displacement field and an immediate field. The displacement field can include a displacement value of up to 32 bits and the immediate field can include an immediate value of up to 32 bits. In order to generate 64 bit displacement and immediate values, the 32 bit value from the displacement field of an instruction and the 32 bit value from the immediate field of the instruction may be concatenated to generate a 64 bit concatenated value. The concatenated value may be used by an execution core as a 64 bit displacement or immediate value as specified by the instruction. By concatenating values from the displacement field and immediate field of an instruction, 64 bit displacement and immediate values may be generated without altering an existing instruction format and without the need for additional instructions. In addition, existing decode logic may advantageously be adapted to allow 64 bit displacement and immediate values to be generated.
In one embodiment, a processor may operate in a 32/64 mode where the default operand size is 32 bits and the default address size is 64 bits. In this embodiment, an instruction may specify a 64 bit displacement value by including 32 bits of the displacement value in the displacement field of the instruction and the remaining 32 bits of the displacement value in the immediate field of the instruction. The two 32 bit values may be concatenated to form the 64 bit displacement value and may be conveyed to an address generation unit. In 32/64 mode, an instruction may specify a 64 bit immediate by using an instruction prefix to override the default operand size of 32 bits. The operating mode may transition the operand size to 64 bits in response to the prefix. The instruction may specify a 64 bit immediate value by including 32 bits of the immediate value in the displacement field of the instruction and the remaining 32 bits of the immediate value in the immediate field of the instruction. The two 32 bit values may be concatenated to form the 64 bit immediate value and may be conveyed to a functional unit.